The present invention relates to a semiconductor memory device, and more particularly, to a technology effectively applicable to readout of a semiconductor memory device in which a number of memory cells are connected to one bit line and the bit line capacitance is large.
In general, nonvolatile memories such as mask ROMs, PROMs and EPROMs store information by setting each memory cell at either of two states allowing and not allowing current flow between its source and drain when a read voltage is applied.
FIG. 7 shows an exemplary configuration of a mask ROM. A memory 700 includes a memory cell array 102 having memory cells arranged in a matrix. FIG. 8 shows a specific circuit configuration of the memory cell array 102, in which memory cells MC are arranged in a matrix. The gates of memory cells MC in the same rows are commonly connected to same word lines WL0 to WLn. The drains of particular memory cells among memory cells MC in the same columns are commonly connected to same bit lines BL0 to BLm according to data stored in the memory cells. That is, memory cells MC whose drains are connected to the bit lines are memory cells storing data “1”, while memory cells whose drains are not connected to the bit lines store data “0”. The sources of the memory cells MC are commonly connected and grounded. With this connection of the memory cells MC, when a read voltage is applied to a selected word line WL and bit line BL to read data stored in a selected memory cell, a memory cell current flows from the bit line BL to the ground potential via the memory cell MC if the drain of the memory cell MC is connected to the bit line. If the drain of the memory cell MC is open, no current path occurs from the bit line BL to the ground potential. By determining the current flowing to the selected bit line, data stored in the selected memory cell can be read.
In FIG. 7, a row decoder 108 selects one of the word lines WL running in the memory cell array 102 in response to a row address received externally, and applies a read voltage to the gate electrodes of memory cells MC 102-1 to 102-8. A column decoder 110 outputs bit line selection signals Ysel_0 to Ysel_k for driving a column selection gate 104 in response to a column address received externally. Selection transistors 104-1 to 104-8 in the column selection gate 104, which are driven with the bit line selection signals Ysel_0 to Ysel_k, selectively connect the bit lines connected to the drains of the memory cells MC 102-1 to 102-8 to read determination circuits 114-1 and 114-2.
Read operation for data stored in the selected memory cells MC will be described with reference to FIG. 9. In FIG. 9, ADD denotes an input address signal. In response to an address change with input of address A0 at time t1, the row decoder 108 selects a particular word line, the column decoder 110 activates a particular bit line selection signal Ysel for selecting a particular bit line, and a controller (not shown) in the memory generates a precharge signal PR. On receipt of this precharge signal, precharge transistors 112-1 to 112-3 precharge read nodes NRED-1 and NRED-2 connected to inputs of the read determination circuits 114-1 and 114-2 and a reference input node NREF as the other input of each of the read determination circuits 114-1 and 114-2 to a predetermined potential as shown by NRED/NREF in FIG. 9. In this precharge of the read nodes NRED-1 and NRED-2 to the potential shown, the bit lines BL selected by the column selection gate 104 in response to the bit line selection signal Ysel are also precharged. Once the precharge operation is terminated at time t2, the potentials of the read nodes NRED-1 and NRED-2 are discharged according to cell currents at the selected memory cells. Note herein that two types of memory cells 102, one allowing and the other not allowing current flow, exist depending on whether or not the drain terminal of the memory cell is connected to a bit line. If a memory cell MC whose drain is connected to a bit line BL is selected, the charge stored under the precharge operation is discharged with the memory cell current at and after the time t2. The potential therefore changes over time as indicated by 204. If a memory cell MC whose drain is open is selected, the charge stored under the precharge operation is kept as it is, and thus the potential is as indicated by 202. The potential of the reference node NREF, configured to be discharged with a reference current set at a half of the memory cell current, lies in the middle between the read node potentials 202 and 204, as indicated by 206 in FIG. 9. Sout denotes an output waveform of the read determination circuit 114-1 or 114-2. Read data Sout(S0) is finalized at the time when the potential difference between the read node potential 202 or 204 and the reference potential 206 reaches a value required for stable read operation in the read determination circuits 114-1 and 114-2. At timing t3 at which the read data Sout(S0) from the read determination circuits 114-1 and 114-2 is finalized, a signal DL inputted into clock terminals Cp of latch circuits 118-1 and 118-2 is lowered, to allow the read data from the read determination circuits 114-1 and 114-2 to be latched by the latch circuits 118-1 and 118-2. Output data Dout(D0) is then outputted from the latch circuits 118-1 and 118-2.
Once the latching of the output of the read determination circuits 114-1 and 114-2 by the latch circuits 118-1 and 118-2 is completed, the bit line selection signal Ysel is made “L”, releasing the selection of the bit lines and inactivating the read determination circuits 114-1 and 114-2. At the same time, a signal DIS goes “H”, and with this, residual charge in the selected bit lines is discharged with transistors 702-1 to 702-8 in a bit line reset circuit 702. The signal DIS is made “L” at the timing of completion of the discharge, to terminate the discharge operation. In this way, one cycle of read operation is completed.
At time t4, an address for next read is inputted, and the read operation cycle described above is repeated.
As described above, in the read method in which the capacitances connected to the read node including a selected bit line and to the reference node are precharged and then discharged with the memory cell current and the reference current to perform readout, residual charge in the selected bit line and the reference node must be discharged after data stored in the memory cell has been read. When all memory cells connected to a selected word line have data “0” and the bit lines are sequentially selected to perform readout, the precharged data will remain in all the bit lines unless post-read bit line discharge is performed. If the address changes in this state to select a word line connected with memory cells MC all having data “1”, the residual charge in the bit lines will be discharged at one time via the memory cells MC, causing a malfunction due to noise. To avoid this problem, post-read bit line discharge is performed every read cycle.
In view of the above, the read cycle in the read method described above includes the precharge time and the discharge time in addition to the operation time for memory cell selection by the row decoder 108, the column decoder 110 and the like and the determination time in the read determination circuits 114.
A technology of shortening the precharge time and the discharge time to speed up the read cycle is disclosed in Japanese Laid-Open Patent Publication No. 2002-216488. FIG. 10 shows an exemplary circuit configuration based on the disclosed technology, in which components identical in circuit operation to those in FIG. 7 are denoted by the same reference numerals. A memory 1000 is different from the configuration in FIG. 7 in that bit line reset transistors in a bit line reset circuit 1102 connected to the bit lines BL are controlled, not with the common control signal DIS, but with a plurality of control signals Res0 to Res3. In this example, control is made so that residual charge in a bit line read in a given read cycle is discharged in parallel with the read operation in the next read cycle.
The operation will be described with reference to FIG. 11. In response to an address change with input of address A0 at time t1, the row decoder 108 selects a particular word line, and the column decoder 110 activates a bit line selection signal Ysel_0 corresponding to the address A0. Read operation like the operation described with reference to FIGS. 7 and 8 is performed for a selected memory cell connected to a bit line selected with the bit line selection signal Ysel_0. Data Sout(S0) read by the read determination circuit 114 under the read operation is latched by the latch circuit 118, and data Dout(D0) is outputted. Once the latching of the output of the read determination circuit 114 by the latch circuit 118 is completed, the bit line selection signal Ysel_0 is made “L”, releasing the bit line selection and inactivating the read determination circuit 114 to terminate the read operation.
Once the read operation in this cycle is terminated, the address input signal is changed to A1 to start read operation in the next cycle at time t4. Upon receipt of address A1, the column decoder 110 activates a bit line selection signal Ysel_1 corresponding to the address A1. A memory cell connected to a bit line selected with the bit line selection signal Ysel_1 is read. In parallel with this read operation, a reset signal Res0 is made “H”, to discharge residual charge in the bit line read in the previous read cycle.
As described above, in the technology disclosed in the patent literature described above, the read cycle can be sped up by performing the bit line residual discharge following the termination of the read operation in parallel with the read operation in the next cycle.
However, a problem arises in the control of the parallel operation of the bit line residual discharge in a given read cycle with the read operation in the next cycle. Since the bit line residual discharge is performed after the address is changed and the read operation in the next cycle is started, the read operation in the next cycle and the discharge of residual charge in the previously read bit line are performed simultaneously as in the time period t6 to t5 shown in FIG. 11. If the selected bit line in a read cycle and the selected bit line in the next read cycle are adjacent to each other, the potentials of the adjacent bit lines may vary during the read determination operation, resulting in affecting the read determination operation due to noise via coupling capacitance. This may block stable read operation.